In modern integrated circuits (ICs) such as microprocessors, it is getting ever more difficult to constrain power supply noise due to among other things circuit switching. For example clock gating is a popular approach to control average power consumption. Unfortunately, however, when large sections of a device are switched on or off, a large current change may be incurred thereby provoking a response (e.g., voltage droop) in the power supply network. While circuits driven by clock distribution networks become less capable of operating at higher frequencies during such droops, clock generators such as phase locked loop (PLL) frequency generators may be designed to continue operating at their target frequencies. To redress this incongruity, some traditional solutions involve operating the clock generator at an overall reduced target frequency so that clock driven circuits can suitably operate during such droops. A novel approach may be desired.